EPM3032ALC44-10N vs EPM3032A-TC44-10N Comparación
Comparación detallada lado a lado de EPM3032ALC44-10N por Altera y EPM3032A-TC44-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3032ALC44-10N | EPM3032A-TC44-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,94 | $5,40 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 600 gates | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | — |
| User I/O Pins | 34 | 34 |
| Propagation Delay (tPD) | 10 ns | — |
| Internal fMAX | 103.1 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Yes, IEEE 1149.1 compliant | — |
| Encapsulado | 44-pin PLCC (J-Lead, surface mount) | 44-pin TQFP |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial range] | [DATA_NEEDED: operating temperature range] |
| Estado RoHS | [DATA_NEEDED: compliant or non-compliant] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Altera (now Intel) |
| Series | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 600 |
| Logic Elements / LABs | — | 2 Logic Array Blocks |
| Número de pines | — | 44 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (commercial speed grade) |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Programming Technology | — | EEPROM (in-system programmable via JTAG / IEEE 1532) |
| Output Enables | — | 6 global OE signals |
| Process Technology | — | CMOS EEPROM |