EPM3064ALC44-7N vs EPM3064ATC44-10N Comparación
Comparación detallada lado a lado de EPM3064ALC44-7N por Intel y EPM3064ATC44-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM3064ALC44-7N - 64-Macrocell MAX 3000A CPLD, 7.5ns, 44-PLCC | Intel / Altera
EPM3064ALC44-7N ⚠ Última compra
Comparación de especificaciones
| Parámetro | EPM3064ALC44-7N | EPM3064ATC44-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3,95 | $5,10 |
| Family | MAX 3000A | MAX 3000A |
| Logic IC Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 2 | 4 |
| Usable Gates | 1,250 | 1250 |
| Number of User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Frequency | 135.1 MHz | — |
| Core Technology | CMOS EEPROM | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Tolerance | 5 V-tolerant | — |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) | — |
| Encapsulado | 44-pin PLCC | TQFP-44 (10x10 mm) |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Programming Software | Quartus II / Quartus Prime (legacy MAX+PLUS II supported) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 64 |
| User I/O Pins | — | 34 |
| Maximum Counter Frequency | — | 192.3 MHz |
| I/O Standard | — | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) compliant |
| Pin-Locking | — | Yes (across design iterations) |