EPM3064AT100-10N vs EPM3064ATC-100-10N Comparación
Comparación detallada lado a lado de EPM3064AT100-10N por Altera y EPM3064ATC-100-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3064AT100-10N | EPM3064ATC-100-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,45 | $2,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | 2 |
| Usable Gates | 1,250 | — |
| User I/O Pins | 66 | 66 |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Bank Voltage | 3.3 V | — |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | 4-pin JTAG (TCK/TMS/TDI/TDO) |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | — |
| Encapsulado | TQFP-100 (T100), 14 mm x 14 mm | TQFP-100 |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Macro Cells | — | 64 |
| Usable Gates (min) | — | 600 |
| Usable Gates (typical) | — | 1,250 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| In-System Programmability | — | Yes (IEEE 1532 / JTAG 1149.1) |
| Tipo de montaje | — | Surface Mount |
| Temperatura de funcionamiento | — | 0C to +70C (commercial) |