EPM3064AT100-10N vs EPM3064ATI100-10N Comparación
Comparación detallada lado a lado de EPM3064AT100-10N por Altera y EPM3064ATI100-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3064ATI100-10N - MAX 3000A CPLD, 64-Macrocell, 100-TQFP | Altera
EPM3064ATI100-10N ✓ ActivoComparación de especificaciones
| Parámetro | EPM3064AT100-10N | EPM3064ATI100-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,45 | $9,80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 66 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Bank Voltage | 3.3 V | — |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | — |
| Encapsulado | TQFP-100 (T100), 14 mm x 14 mm | 100-pin TQFP (industrial) |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | RoHS Non-Compliant |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Programmable Type | — | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM |
| User I/O | — | 66 |
| Supply Voltage (Core / I/O) | — | 3.3 V |
| Pin-to-Pin Delay (tPD) | — | 10 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz (counter) |
| Temperatura de funcionamiento | — | -40 C to +85 C (industrial) |
| JTAG (IEEE 1149.1) | — | Yes |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) |
| MultiVolt I/O | — | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing |
| Lead-Free Status | — | Contains Lead |