EPM3064ATC100-10 vs EPM3064ATC100-7 Comparación
Comparación detallada lado a lado de EPM3064ATC100-10 por Altera y EPM3064ATC100-7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 NrndAltera
EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera
EPM3064ATC100-7 ObsoleteComparación de especificaciones
| Parámetro | EPM3064ATC100-10 | EPM3064ATC100-7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $2,85 | $3,08 |
| Family | MAX 3000A | MAX 3000A |
| Logic Gates | 1250 gates | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks | 2 | — |
| User I/O Pins | 34 | — |
| Encapsulado | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin TQFP |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant | — |
| Global Clock Signals | 2 (with optional inversion) | — |
| Output Enable Signals | 6 or 10 pin- or logic-driven | — |
| Output Slew-Rate Control | Programmable | — |
| Operating Temperature Grade | Commercial | — |
| MultiVolt I/O Support | 1.5V / 1.8V / 2.5V / 3.3V interfaces | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Usable Gates | — | 1,250 |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/Os | — | 66 (in 100-pin TQFP) |
| Pin-to-Pin Propagation Delay (tPD) | — | 7.5 ns (-7 speed grade) |
| Maximum Internal Counter Frequency | — | 135.1 MHz |
| Supply Voltage - VCCINT (Core) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Technology | — | CMOS EEPROM |
| Tipo de montaje | — | Surface Mount |
| Temperatura de funcionamiento | — | 0C to +70C (commercial) |
| In-System Programming (ISP) | — | Yes, via IEEE 1149.1 JTAG |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 |
| JTAG Boundary Scan | — | Yes |
| Lead Free / RoHS | — | Compliant (modern shipments) |