EPM3064ATC100-10 vs EPM3064ATI100-10 Comparación
Comparación detallada lado a lado de EPM3064ATC100-10 por Altera y EPM3064ATI100-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 NrndComparación de especificaciones
| Parámetro | EPM3064ATC100-10 | EPM3064ATI100-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $2,85 | $6,80 |
| Family | MAX 3000A | MAX 3000A |
| Logic Gates | 1250 gates | — |
| Macrocells | 64 | — |
| Logic Array Blocks | 2 | — |
| User I/O Pins | 34 | — |
| Encapsulado | TQFP-100 (100-pin Thin Quad Flat Pack) | 100-pin TQFP |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant | — |
| Global Clock Signals | 2 (with optional inversion) | — |
| Output Enable Signals | 6 or 10 pin- or logic-driven | — |
| Output Slew-Rate Control | Programmable | — |
| Operating Temperature Grade | Commercial | Industrial |
| MultiVolt I/O Support | 1.5V / 1.8V / 2.5V / 3.3V interfaces | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Non-Compliant |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | — | 64 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Number of User I/Os | — | 66 |
| Usable Gates | — | 1,250 |
| Tensión de alimentación | — | 3.3 V |
| Speed Grade | — | -10 (10 ns pin-to-pin) |
| Programmable Type | — | In-System Programmable (EEPROM) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| Tipo de montaje | — | Surface Mount |
| Lead Free Status | — | Contains Lead |