EPM3064ATC44-7N vs EPM3064ATC44-4N Comparación
Comparación detallada lado a lado de EPM3064ATC44-7N por Altera y EPM3064ATC44-4N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3064ATC44-7N | EPM3064ATC44-4N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $2,30 | $3,45 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | 64 |
| Logic Array Blocks | 2 | 2 |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 34 | — |
| Número de pines | 44 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 192.3 MHz (-7 grade) | 222.2 MHz |
| Supply Voltage (VCC) | 3.3 V | — |
| MultiVolt I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Programmability | EEPROM, in-system programmable (ISP) | EEPROM, in-system programmable (JTAG) |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| ISP Standard | IEEE Std. 1532 compliant | — |
| Boundary-Scan Test (BST) | Built-in, JTAG-driven | — |
| Encapsulado | 44-pin TQFP | 44-pin TQFP |
| Temperatura de funcionamiento | 0°C to +85°C (commercial) | 0C to +70C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant | [DATA_NEEDED: rohs status] |
| Number of I/Os | — | 34 |
| Dedicated Inputs | — | 4 |
| Propagation Delay (tpd) | — | 4.5 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V or 3.3 V |
| JTAG Support | — | IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP) |