EPM3064ATI44-4N vs EPM3064ATI44-7N Comparación
Comparación detallada lado a lado de EPM3064ATI44-4N por Altera y EPM3064ATI44-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3064ATI44-4N | EPM3064ATI44-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,25 | $5,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements / Macrocells | 64 macrocells | 64 macrocells |
| Usable Gates | 1,250 gates | 1,250 gates |
| Number of Logic Array Blocks (LABs) | 4 LABs (16 macrocells each) | — |
| Maximum Operating Frequency | 222.2 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 4.5 ns (-4 speed grade) | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | — |
| User I/O Pins | 34 I/O | — |
| Encapsulado | 44-pin TQFP | 44-pin TQFP (10x10 mm, 0.8 mm pitch) |
| Temperatura de funcionamiento | -40C to +85C (industrial) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 ISP | IEEE 1149.1 JTAG |
| Configuration Memory | EEPROM (non-volatile) | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | Compliant (lead-free, 'N' suffix) |
| Maximum Frequency (fMAX) | — | 135.1 MHz |
| Pin-to-Pin Logic Delay | — | 7 ns (speed grade -7) |
| User I/O Count | — | 34 I/O |
| Dedicated Input Pins | — | 4 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Bank Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5 V tolerant (multiVolt) |
| Program Memory Type | — | EEPROM (in-system programmable) |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Process Technology | — | 0.30 µm CMOS EEPROM |