EPM3128ATC144-10N vs EPM3128ATC144-5N Comparación
Comparación detallada lado a lado de EPM3128ATC144-10N por Intel y EPM3128ATC144-5N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3128ATC144-10N | EPM3128ATC144-5N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,56 | $13,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 (up to 10,000 for full family) | 2500 |
| Logic Array Blocks (LABs) | 8 | — |
| User I/Os | 96 | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Counter Frequency (fCNT) | 98 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V | — |
| MultiVolt I/O Support | 3.3 V / 2.5 V / 1.8 V | — |
| Configuration Memory | EEPROM (in-system programmable, non-volatile) | — |
| Encapsulado | 144-pin TQFP | 144-pin TQFP (20x20 mm) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0C to 70C (Commercial) |
| JTAG (IEEE 1149.1) | Yes (BST + pin-locking) | — |
| ISP (IEEE 1532) | Yes | — |
| Logic Family | — | CMOS |
| Macrocells | — | 128 |
| User I/O | — | 96 |
| Pin-to-Pin Logic Delay | — | 5 ns |
| Counter Frequency | — | up to 227.3 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Logic Levels Supported | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| In-System Programmability | — | Yes (3.3-V via JTAG) |
| JTAG Boundary Scan | — | IEEE Std 1149.1 compliant |
| Estado RoHS | — | Compliant (lead-free) |