EPM3128ATC144-7N vs EPM3256ATC144-7N Comparación
Comparación detallada lado a lado de EPM3128ATC144-7N por Altera y EPM3256ATC144-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3128ATC144-7N | EPM3256ATC144-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,25 | $17,20 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Architecture | EEPROM-based, MAX architecture | — |
| Number of Macrocells | 128 | — |
| Number of Usable Gates | Up to 10,000 | — |
| User I/Os | 96 | 116 |
| Recuento de pines | 144 | — |
| Encapsulado | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | 144-pin TQFP |
| Logic Family | CMOS | CMOS |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | 7.5 ns |
| Counter Frequency | Up to 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0C to +70C (Commercial) |
| In-System Programmability (ISP) | Yes, via JTAG (IEEE 1149.1) | — |
| PCI Compliance | Compatible with PCI Local Bus Specification Rev. 2.2 | — |
| Tipo de montaje | Surface Mount (SMD/SMT) | Surface Mount |
| Estado RoHS | Lead-free (-7N suffix indicates Pb-free finish) | Compliant |
| Family | — | MAX 3000A |
| Macro Cells | — | 256 |
| Logic Gates (usable) | — | 5,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Maximum Internal Frequency | — | 126.6 MHz |
| Supply Voltage (VCCIO) | — | 3.0 V to 3.6 V |
| Programmable Logic Technology | — | CMOS EEPROM-based |
| In-System Programmable (ISP) | — | Yes (3.3 V) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |