EPM3128ATI144-10 vs EPM3128ATI144-7N Comparación
Comparación detallada lado a lado de EPM3128ATI144-10 por Altera y EPM3128ATI144-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3128ATI144-10 - MAX 3000A CPLD 128 Macro 98 I/O TQFP-144 | Intel/Altera
EPM3128ATI144-10 NrndAltera
EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A
EPM3128ATI144-7N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM3128ATI144-10 | EPM3128ATI144-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,85 | $9,95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 2,500 | — |
| Macro Cells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| User I/Os | 98 | — |
| Recuento de pines | 144 | — |
| Encapsulado | TQFP-144 (FINE LINE) | 144-pin TQFP |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Counter Frequency | 98 MHz typical | — |
| Logic Family | CMOS, EEPROM-based | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | JTAG (IEEE Std 1149.1) in-system programmable |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10) | — |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount (Gull-Wing TQFP) | — |
| Estado RoHS | Compliant (lead-free TQFP) | — |
| Logic Capacity | — | 2.5K gates |
| Macrocells | — | 128 |
| Maximum Frequency (fMAX) | — | 129.9 MHz |
| Pin-to-Pin Propagation Delay | — | 7.5 ns (speed grade -7) |
| User I/O Pins | — | 96 |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V / 1.8 V |
| Programmable Logic Technology | — | CMOS EEPROM |
| Terminal Pitch | — | 0.5 mm |
| JEDEC Package Code | — | S-PQFP-G144 |
| MultiVolt I/O | — | Yes (interfaces with 5.0V/3.3V/2.5V/1.8V logic) |