EPM3256AFC256-10 vs EPM3256AFC256-7 Comparación
Comparación detallada lado a lado de EPM3256AFC256-10 por Altera y EPM3256AFC256-7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM3256AFC256-10 | EPM3256AFC256-7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,95 | $12,10 |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 256 |
| Usable Gates | 5,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 (16 macrocells each) | 16 |
| Maximum User I/Os | 161 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 95.2 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V tolerant | — |
| In-System Programmability | Yes (3.3 V ISP via JTAG IEEE 1149.1) | IEEE Std. 1532-compliant 3.3-V ISP |
| Temperatura de funcionamiento | 0°C to +70°C (Commercial) | 0 °C to 70 °C (Commercial) |
| Encapsulado | 256-ball FBGA (Fine-Line BGA) | FBGA-256 (FineLine BGA), 256 balls |
| Pitch | [DATA_NEEDED: BGA ball pitch] | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| User I/Os | — | 161 |
| Pin-to-Pin Logic Delay | — | 4.5 ns (max) |
| Counter Frequency | — | 227.3 MHz (max) |
| Propagation Delay (tpd) | — | 10 ns |
| Core Voltage | — | 3.3 V |
| I/O Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) |
| Process Technology | — | CMOS EEPROM, 0.30 µm |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| Speed Grade | — | -7 |