EPM3256AFC256-10N vs EPM3256AFC256-7 Comparación
Comparación detallada lado a lado de EPM3256AFC256-10N por Altera y EPM3256AFC256-7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3256AFC256-10N | EPM3256AFC256-7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $25,95 | $12,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5,000 gates | 10,000 |
| Macrocells | 256 | — |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | 4.5 ns (max) |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | 3.3 V |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| Encapsulado | 256-pin FineLine BGA | FBGA-256 (FineLine BGA), 256 balls |
| Logic Family | CMOS | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| Temperatura de funcionamiento | 0 C to 70 C (commercial) | 0 °C to 70 °C (Commercial) |
| Macro Cells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/Os | — | 161 |
| Counter Frequency | — | 227.3 MHz (max) |
| Propagation Delay (tpd) | — | 10 ns |
| I/O Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) |
| Process Technology | — | CMOS EEPROM, 0.30 µm |
| In-System Programmability | — | IEEE Std. 1532-compliant 3.3-V ISP |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| Speed Grade | — | -7 |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance status] |