EPM3256AQC208-10N vs EPM3256AFC256-10N Comparación
Comparación detallada lado a lado de EPM3256AQC208-10N por Altera y EPM3256AFC256-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3256AQC208-10N | EPM3256AFC256-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,62 | $25,95 |
| Series | MAX 3000A | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements/Blocks | 16 LABs | — |
| Usable Gates | 10,000 | 5,000 gates |
| Number of I/O Pins | 161 (158 user I/O per Arrow listing) | — |
| Propagation Delay (tpd) | 10 ns (max) | — |
| Maximum Counter Frequency | 227.3 MHz | 227.3 MHz |
| Supply Voltage - Internal | 3.0 V to 3.6 V (3.3 V typical) | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0 C to 70 C (commercial) |
| Encapsulado / Carcasa | 208-BFQFP / 208-PQFP (28x28 mm) | — |
| Tipo de montaje | Surface Mount | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| I/O Tolerance | 5 V tolerant, MultiVolt interface | — |
| Estado RoHS | [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] | — |
| Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 256 |
| Maximum User I/O | — | 161 |
| Pin-to-Pin Logic Delay | — | 10 ns |
| Core Voltage | — | 3.3 V |
| I/O Logic Level Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) |
| Encapsulado | — | 256-pin FineLine BGA |
| Logic Family | — | CMOS |
| PCI Compliance | — | PCI Local Bus Specification Rev 2.2 (at -10 grade) |