EPM3256ATC144-10N vs EPM3256AT1144-10S Comparación
Comparación detallada lado a lado de EPM3256ATC144-10N por Altera y EPM3256AT1144-10S por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Última compra
Comparación de especificaciones
| Parámetro | EPM3256ATC144-10N | EPM3256AT1144-10S |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,50 | $21,30 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 (up to 10,000 usable in family) | — |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Encapsulado | 144-LQFP (TQFP, ATC suffix) | TQFP-144 |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | 0C to +85C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage - Core | — | 3.3 V |
| I/O Voltage Support | — | 2.5V / 3.3V / 5.0V MultiVolt |
| Programmable Interconnect | — | EEPROM-based, non-volatile |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG |
| Configuration Cells | — | EEPROM (instant-on, no external PROM) |