EPM3512AFC256-10 vs EPM3512AFC256-2 Comparación
Comparación detallada lado a lado de EPM3512AFC256-10 por Altera y EPM3512AFC256-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AFC256-10 | EPM3512AFC256-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,50 | $14,85 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 10,000 | — |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | — |
| Encapsulado | 256-pin FBGA | BGA-256 (FineLine BGA) |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| Recuento de pines | 256 | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| Maximum User I/O Pins | — | 212 |
| Propagation Delay (tPD, -2 grade) | — | [DATA_NEEDED: tPD ns] |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX MHz] |
| Core Supply Voltage | — | 3.3 V |
| I/O Output Drive Voltage | — | 2.5 V or 3.3 V (MultiVolt) |
| Input Tolerance | — | 2.5 V, 3.3 V, 5.0 V tolerant |
| Ball Pitch | — | 1.0 mm |
| Programming Interface | — | JTAG (IEEE Std 1149.1) / ByteBlaster |
| Process Technology | — | 0.30 um CMOS EEPROM |
| Temperatura de funcionamiento | — | 0C to +70C (commercial) |
| Speed Grade | — | -2 |