EPM3512AFI256-10N vs EPM3512AFI256-10 Comparación
Comparación detallada lado a lado de EPM3512AFI256-10N por Altera y EPM3512AFI256-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM3512AFI256-10N | EPM3512AFI256-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,75 | $18,75 |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | — |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | 227.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | Yes, IEEE Std. 1532 (3.3 V ISP) |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| Encapsulado | 256-ball FineLine BGA (FBGA-256) | FBGA-256 (FineLine BGA, 256 balls) |
| Tipo de montaje | Surface Mount | — |
| Rango de temperatura de funcionamiento | -40 °C to +85 °C (industrial) | — |
| Estado RoHS | Compliant | [DATA_NEEDED: rohs_status] |
| Speed Grade | -10 (10 ns tPD) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Equivalent Gates | — | 10,000 |
| Macrocells | — | 512 |
| User I/Os | — | 208 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.5 ns |
| Propagation Delay | — | 7.5 ns (max, per chipdig summary) |
| Core Voltage | — | 3.3 V |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V |
| Process Technology | — | CMOS EEPROM |
| Temperatura de funcionamiento | — | 0C to +70C (commercial) |
| Logic Family | — | CMOS |
| Tensión de alimentación | — | 3.3 V (core); MultiVolt I/O to 5.0 V |