EPM3512AQC208-10-10N vs EPM3512AQC208-10 Comparación
Comparación detallada lado a lado de EPM3512AQC208-10-10N por Altera y EPM3512AQC208-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N ObsoleteComparación de especificaciones
| Parámetro | EPM3512AQC208-10-10N | EPM3512AQC208-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $31,20 | $22,10 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| User I/Os | 172 | 208 |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | 7.5 ns |
| Maximum Frequency (fCNT) | 87 MHz | 116.3 MHz |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | Yes (IEEE Std. 1532) |
| Boundary-Scan (JTAG) | Yes, IEEE 1149.1 | — |
| PCI-SIG Compliance | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) | — |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0C to +70 C (commercial) |
| Encapsulado | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP |
| Tipo de montaje | Surface Mount | — |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Array Blocks (LABs) | — | 32 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |
| Estado RoHS | — | [DATA_NEEDED: RoHS status not in verified data] |