EPM3512AQC208-10 vs EPM3512AQC208-10N Comparación
Comparación detallada lado a lado de EPM3512AQC208-10 por Altera y EPM3512AQC208-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AQC208-10 | EPM3512AQC208-10N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,10 | $42,80 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 10,000 | Up to 10,000 |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 32 | 16 |
| User I/Os | 208 | 172 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE Std. 1532) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) | — |
| Encapsulado | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| Temperatura de funcionamiento | 0C to +70 C (commercial) | 0 C to 70 C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status not in verified data] | [DATA_NEEDED: RoHS status not in verified web data] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Tensión de alimentación | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| Speed Grade | — | -10 |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |