EPM3512AQC208-10 vs EPM3512AQC208-10NS Comparación
Comparación detallada lado a lado de EPM3512AQC208-10 por Altera y EPM3512AQC208-10NS por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AQC208-10 | EPM3512AQC208-10NS |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,10 | $32,40 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 10,000 | 10,000 |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 32 | 12 |
| User I/Os | 208 | 172 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE Std. 1532) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) | — |
| Encapsulado | 208-pin PQFP | 208-pin PQFP |
| Temperatura de funcionamiento | 0C to +70 C (commercial) | 0C to +70C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status not in verified data] | [DATA_NEEDED: rohs status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Counter Frequency | — | 227.3 MHz max |
| Propagation Delay | — | 7.5 ns (datasheet figure) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Logic Family | — | CMOS, EEPROM-based |
| Configuration | — | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) |
| ISP Standard | — | IEEE Std. 1532 |
| Tipo de montaje | — | Surface Mount |