EPM3512AQC208-10N vs EPM3512AQC20-10 Comparación
Comparación detallada lado a lado de EPM3512AQC208-10N por Intel y EPM3512AQC20-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AQC208-10N | EPM3512AQC20-10 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $42,80 | $21,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | Up to 10,000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/Os | 172 | — |
| Encapsulado | 208-pin PQFP (Plastic Quad Flat Pack) | PQFP-240 (QC20 designation per Altera ordering code) |
| Tensión de alimentación | 3.3 V | — |
| Pin-to-Pin Delay | 4.5 ns (-10 speed grade) | — |
| Maximum Internal Frequency | 227.3 MHz | — |
| Speed Grade | -10 | — |
| Process Technology | CMOS EEPROM | 0.30 µm EEPROM CMOS |
| In-System Programming | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| I/O Standards | MultiVolt (1.8V / 2.5V / 3.3V) | — |
| Temperatura de funcionamiento | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status not in verified web data] | Compliant (lead-free PQFP package) |
| Macrocells per LAB | — | 32 |
| User I/O Pins | — | 100 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage VCCINT | — | 5.0 V |
| MultiVolt I/O Voltages | — | 5.0 V / 3.3 V / 2.5 V / 1.8 V |
| Programming Interface | — | IEEE 1149.1 (JTAG) - In-System Programmable |