EPM3512AQC208-10NS vs EPM3512AQ208-10N Comparación
Comparación detallada lado a lado de EPM3512AQC208-10NS por Altera y EPM3512AQ208-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera
EPM3512AQ208-10N ✓ ActivoComparación de especificaciones
| Parámetro | EPM3512AQC208-10NS | EPM3512AQ208-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $32,40 | $21,40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 12 | 32 |
| User I/Os | 172 | 172 |
| Pin-to-Pin Delay (tPD) | 10 ns (speed grade -10) | 4.5 ns (typical) |
| Internal Counter Frequency | 227.3 MHz max | — |
| Propagation Delay | 7.5 ns (datasheet figure) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | 2.5 V, 3.3 V, or 5.0 V |
| Logic Family | CMOS, EEPROM-based | — |
| Configuration | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) | — |
| Encapsulado | 208-pin PQFP | 208-pin PQFP |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| ISP Standard | IEEE Std. 1532 | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | unknown |
| Tipo de montaje | Surface Mount | Surface Mount |
| Macrocells | — | 512 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Maximum Frequency (fCNT) | — | 227.3 MHz |
| Process Technology | — | CMOS EEPROM |
| Programming Interface | — | IEEE Std. 1532 (JTAG) ISP |
| Operating Temperature (Industrial) | — | -40 C to +85 C |