EPM3512AQC208-7N vs EPM3512AQC208-10 Comparación
Comparación detallada lado a lado de EPM3512AQC208-7N por Altera y EPM3512AQC208-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM3512AQC208-7N | EPM3512AQC208-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $41,41 | $22,10 |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 512 macrocells, 10,000 usable gates | — |
| Logic Array Blocks (LABs) | 32 | 32 |
| Macrocells per LAB | 16 | — |
| User I/Os | 172 | 208 |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns |
| Maximum Frequency (fCNT) | 116.3 MHz | 116.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | 3.3 V |
| I/O Bank Count | 4 (MultiVolt) | — |
| Supported I/O Standards | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Configuration | Non-volatile EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1149.1 BST + IEEE 1532 ISP | — |
| Encapsulado | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) | 208-pin PQFP |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0C to +70 C (commercial) |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS status not in verified data] |
| Speed Grade | -7 | — |
| Usable Gates | — | 10,000 |
| Macrocells | — | 512 |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |