EPM3512AQI208-7 vs EPM3512AQC208-7N Comparación
Comparación detallada lado a lado de EPM3512AQI208-7 por Altera y EPM3512AQC208-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM3512AQI208-7 | EPM3512AQC208-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $41,41 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 10,000 | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 32 |
| Maximum Operating Frequency | 116.3 MHz | — |
| Speed Grade | -7 | -7 |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD in ns] | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | — |
| Programmability | Non-volatile, in-system programmable (IEEE Std. 1532) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan + ISP) | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for PQFP-208] | — |
| Encapsulado | 208-pin PQFP | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0 °C to +70 °C (commercial) |
| Lead-Free / RoHS | Compliant per Altera product page | — |
| Logic Capacity | — | 512 macrocells, 10,000 usable gates |
| Macrocells per LAB | — | 16 |
| User I/Os | — | 172 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Count | — | 4 (MultiVolt) |
| Supported I/O Standards | — | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Configuration | — | Non-volatile EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1149.1 BST + IEEE 1532 ISP |
| Estado RoHS | — | Compliant |