EPM5016DI-20 vs EPM5016PC-1 Comparación
Comparación detallada lado a lado de EPM5016DI-20 por Altera y EPM5016PC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5016DI-20 | EPM5016PC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,50 | $9,95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (UV-erasable CMOS) | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 20 ns | 35 ns |
| Frecuencia de reloj máxima | 62.5 MHz | — |
| Total Inputs | 16 | — |
| Dedicated Inputs | 7 | — |
| Configurable I/O Pins | 8 | — |
| External Clock Inputs | 1 | — |
| Product Terms per Output | 8 | — |
| Output Functions per Macrocell | 8 | — |
| Technology | CMOS EPROM | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| Encapsulado | 20-pin Ceramic DIP (DI), windowed | PDIP-20 (plastic DIP, through-hole) |
| Speed Grade | -20 (20 ns tPD) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Tensión de alimentación | [DATA_NEEDED: VCC nominal] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (PDIP with SnPb leads, pre-RoHS era) |
| Usable Gates | — | 200 |
| Logic Array Blocks (LABs) | — | 1 |
| Maximum Frequency (fMAX) | — | 62 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time ns] |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Supply Current (ICC) | — | 50 mA typical |
| Recuento de pines | — | 20 |
| Configuration Memory | — | CMOS EEPROM (UV-erasable) |
| Programming Interface | — | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) |