EPM5032DC-25 vs EPM5032DC-15 Comparación
Comparación detallada lado a lado de EPM5032DC-25 por Altera y EPM5032DC-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 ObsoleteComparación de especificaciones
| Parámetro | EPM5032DC-25 | EPM5032DC-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3,55 | $9,95 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | UV-erasable EPLD (PAL-type CMOS) |
| Macrocells | 32 | 32 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Counter Frequency (fCNT) | [DATA_NEEDED: maximum counter frequency] | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Number of Dedicated Inputs | 32 (in DIP-28 pinout) | — |
| Number of I/O Pins | 22 (in DIP-28 pinout, 4 used as dedicated inputs) | — |
| Encapsulado | CDIP-28 (Windowed Ceramic DIP-28) | CERDIP-28 (windowed, through-hole) |
| Process Technology | CMOS, EPROM (UV-Erasable) | CMOS |
| Architecture | PAL-Type, Single-LAB, 32-Macrocell | — |
| Output Structure | Programmable I/O with output enable | — |
| Flip-Flop Configuration | D, T, JK, or SR (programmable) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Estado RoHS | Lead Free / RoHS Compliant (per distributor listings) | [DATA_NEEDED: RoHS status] |
| Programming Method | UV erase + Altera/Intel MAX+PLUS II programmer | — |
| Erasure Method | UV light through ceramic window | UV light through ceramic quartz window |
| Family | — | MAX 5000 |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Programmable Pins | — | 16 bidirectional I/O + 4 dedicated input = 20 |
| Total Package Pins | — | 28 |
| Tipo de montaje | — | Through-Hole (DIP) |
| Lead-Free | — | unknown |