EPM5032DC-25 vs EPM5032DC20 Comparación

Comparación detallada lado a lado de EPM5032DC-25 por Altera y EPM5032DC20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.

Comparación de especificaciones

Parámetro EPM5032DC-25 EPM5032DC20
Marca Altera Altera
Categoría FPGA & CPLD FPGA & CPLD
Estado del ciclo de vida NRND Obsolete
Estado del stock In Stock In Stock
Precio unitario (USD) $3,55 $8,20
Manufacturer Altera (Intel Programmable Solutions Group) —
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (EPLD) —
Macrocells 32 32
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Maximum Counter Frequency (fCNT) [DATA_NEEDED: maximum counter frequency] —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Number of Dedicated Inputs 32 (in DIP-28 pinout) —
Number of I/O Pins 22 (in DIP-28 pinout, 4 used as dedicated inputs) —
Encapsulado CDIP-28 (Windowed Ceramic DIP-28) 20-pin Ceramic DIP (DC) with UV window
Process Technology CMOS, EPROM (UV-Erasable) CMOS
Architecture PAL-Type, Single-LAB, 32-Macrocell PAL-type with Programmable Interconnect Array (PIA)
Output Structure Programmable I/O with output enable —
Flip-Flop Configuration D, T, JK, or SR (programmable) —
Temperatura de funcionamiento [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Estado RoHS Lead Free / RoHS Compliant (per distributor listings) [DATA_NEEDED: RoHS compliance]
Programming Method UV erase + Altera/Intel MAX+PLUS II programmer —
Erasure Method UV light through ceramic window —
Device Family — MAX 5000
Product Type — UV-erasable PLD (CPLD class)
Usable Gates — 600
Propagation Delay (tPD) — 20 ns
Maximum Frequency (Fmax) — 71.4 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Dedicated Inputs — 7
I/O Pins — 16 (bidirectional)
Total Inputs (max) — 24
Output Macrocells — 16
Clock Inputs — 1 (global)
Tipo de montaje — Through-Hole (DIP)

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