EPM5032LC-15 vs EPM5032JC-20 Comparación
Comparación detallada lado a lado de EPM5032LC-15 por Altera y EPM5032JC-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5032LC-15 | EPM5032JC-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,20 | $9,75 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Architecture | PAL-type AND/OR with PIA | PAL-type AND-OR array with PIA interconnect |
| Usable Gates | 600 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 4 | 1 |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 16 | — |
| Maximum Operating Frequency | 83.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM, 1.0 um process | — |
| Programmability | UV-Erasable / OTP | — |
| Encapsulado | JLCC-28 (windowed ceramic) | 68-pin JLCC (windowed ceramic) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Estado RoHS | Non-compliant (contains Pb, ceramic-windowed package) | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Product Terms (P-terms) | — | 320 |
| Propagation Delay (tPD) | — | 20 ns |
| Frecuencia de reloj máxima | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Estado del ciclo de vida | — | Obsolete (legacy Altera MAX 5000) |