EPM5032PC-20 vs EPM5032JC-20 Comparación
Comparación detallada lado a lado de EPM5032PC-20 por Altera y EPM5032JC-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5032PC-20 | EPM5032JC-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,05 | $9,75 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Programming Type | OTP (One-Time Programmable) | — |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | — |
| Logic Blocks | 2 Logic Array Blocks | — |
| Product Terms | 320 | — |
| Dedicated Inputs | 24 | 8 |
| Bidirectional I/O Lines | 16 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Frecuencia de reloj máxima | 62.5 MHz | 62.5 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Technology | CMOS, 0.65 um process | — |
| Architecture | PAL-type macrocells with Programmable Interconnect Array (PIA) | PAL-type AND-OR array with PIA interconnect |
| Encapsulado | PDIP-28 (Plastic DIP, 28-pin) | 68-pin JLCC (windowed ceramic) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Tipo de montaje | Through-Hole | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Estado del ciclo de vida | — | Obsolete (legacy Altera MAX 5000) |