EPM5064JI-1 vs EPM5064LC-1 Comparación
Comparación detallada lado a lado de EPM5064JI-1 por Intel y EPM5064LC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5064JI-1 | EPM5064LC-1 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $3,40 | $9,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| User I/O Pins | [DATA_NEEDED: user I/O count from datasheet] | — |
| Encapsulado | 68-pin PLCC (windowed ceramic) | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Logic Elements | [DATA_NEEDED: total logic elements] | — |
| Propagation Delay (tPD) | [DATA_NEEDED: combinational tPD from datasheet] | 40 ns |
| Tensión de alimentación | 5 V | — |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial vs industrial grade temp range] | [DATA_NEEDED: operating temperature range] |
| Process Technology | CMOS, UV-erasable | CMOS |
| Speed Grade | JI-1 (commercial, -10/-12/-15 family) | — |
| Programmability | UV-erasable (windowed package) | — |
| Data Retention | 25 years (per MAX 5000 datasheet) | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | [DATA_NEEDED: not stated in provided data] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| Usable Gates | — | 1.25K (approx.) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Internal Operating Frequency | — | 62.5 MHz |
| Input Lines | — | 36 |
| Dedicated Inputs | — | 7 |
| Output Lines | — | 28 |
| Programming Technology | — | OTP / UV-Erasable EPROM |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |