EPM5128LC2 vs EPM5128JC-2 Comparación
Comparación detallada lado a lado de EPM5128LC2 por Altera y EPM5128JC-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5128LC2 | EPM5128JC-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,40 | $21,75 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable Programmable Logic Device (PLD) |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 dedicated | — |
| Propagation Delay (tPD) | 45 ns | 45 ns (max) |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS EPROM | CMOS |
| Configuration Memory | On-chip EPROM (non-volatile) | — |
| Boundary Scan | JTAG / IEEE 1149.1 | — |
| Temperatura de funcionamiento | -40 C to +85 C (extended commercial) | [DATA_NEEDED: operating temperature range] |
| Encapsulado | PGA (Pin Grid Array, ceramic) | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| Tipo de montaje | Through-Hole / Socketed | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Dedicated Inputs | — | 7 |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| Tensión de alimentación | — | 5 V (nominal) |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |