EPM5130LC vs EPM5130GI Comparación
Comparación detallada lado a lado de EPM5130LC por Altera y EPM5130GI por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5130LC | EPM5130GI |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,60 | $16,20 |
| Series | MAX 5000 | — |
| Family | MAX 5000 (EPM51xx) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| User I/O Pins | 48 | — |
| Total Inputs (Dedicated + I/O) | 68 | — |
| Dedicated Inputs | 19 | 19 |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Internal Clock Frequency | 50 MHz | — |
| Global Clock Inputs | 1 | — |
| Configuration Technology | UV-Erasable / OTP EPROM | — |
| Process Technology | CMOS (0.7 um EPROM) | CMOS |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| I/O Standard | TTL-compatible | — |
| Encapsulado | JLCC-68 (J-Lead Ceramic Chip Carrier) | Ceramic Pin Grid Array (PGA), windowed |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial/industrial/military grade] | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 5000 |
| Architecture | — | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Total Inputs | — | 68 |
| I/O Pins | — | 48 |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| External Clock Pins | — | 1 |
| Tensión de alimentación | — | 5 V |
| Programming Method | — | UV erasure + EPROM programming |