EPM5130WC-2 vs EPM5130QC-1 Comparación
Comparación detallada lado a lado de EPM5130WC-2 por Altera y EPM5130QC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5130WC-2 | EPM5130QC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $62,00 | $9,95 |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable PLD (CPLD) | UV-Erasable / OTP Complex PLD (CPLD) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperatura de funcionamiento | 0 °C to 70 °C (Commercial) | Commercial (0 C to +70 C) |
| Process Technology | CMOS | CMOS |
| Dedicated Inputs | 19 | — |
| User I/O Lines | 48 | — |
| Total Inputs (I/O + dedicated) | 68 | — |
| Package Type | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing | — |
| Terminal Pitch | 0.650 mm | 0.635 mm |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Memory | UV-erasable CMOS EEPROM cells | UV-Erasable EPROM |
| Speed Grade | -2 (45 ns) | -1 |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | AND/OR array with programmable macrocell register | — |
| Family | — | MAX 5000 |
| Logic Cells / Macrocells | — | 128 macrocells |
| Usable Gates (marketing) | — | 5130 gates |
| Encapsulado | — | PQFP-100 (windowed ceramic) |
| Tensión de alimentación | — | 5 V (single) |
| Programmable Polarity | — | Yes (per macrocell) |
| Boundary Scan / JTAG | — | Per MAX 5000 family |