EPM5192-1LC vs EPM5192LC Comparación
Comparación detallada lado a lado de EPM5192-1LC por Altera y EPM5192LC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192-1LC | EPM5192LC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,40 | $28,40 |
| Family | MAX 5000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 4 | 12 |
| User I/O Pins | 64 | 64 |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | — |
| Tensión de alimentación | 5 V | — |
| Process Technology | UV EPROM, erasable windowless | CMOS, UV-erasable/OTP EPROM configuration |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | Programmable Interconnect Array (PIA), fixed delay |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Encapsulado | 64-pin Ceramic J-Lead Chip Carrier (LC) | JLCC-68 (windowed ceramic, LC suffix) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Estado RoHS | Non-compliant (ceramic windowless package, lead-bearing termination) | [DATA_NEEDED: RoHS status] |
| Dedicated Inputs | — | 7 |
| Global Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | — | 0C to +70C |