EPM5192AJC84-20 vs EPM5192AGC84-15 Comparación
Comparación detallada lado a lado de EPM5192AJC84-20 por Altera y EPM5192AGC84-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 Obsolete
Comparación de especificaciones
| Parámetro | EPM5192AJC84-20 | EPM5192AGC84-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,20 | $42,00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | UV-Erasable/OTP Complex PLD |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | — |
| Frecuencia de reloj máxima | 66.7 MHz | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS |
| Encapsulado | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin Ceramic PGA (Pin Grid Array) |
| Operating Temperature Grade | Commercial | — |
| Tipo de montaje | Surface Mount (J-Lead) | Through-Hole |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Internal Clock Frequency | — | 83.3 MHz |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Programmable Element | — | UV-Erasable EPROM cell |
| Temperatura de funcionamiento | — | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] |