EPM5192AQC-2 vs EPM5192AQC100-15 Comparación
Comparación detallada lado a lado de EPM5192AQC-2 por Altera y EPM5192AQC100-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192AQC-2 | EPM5192AQC100-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,50 | $9,95 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | UV-Erasable / OTP Complex PLD (CPLD) |
| Series | MAX 5000 (EPM5192) | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | 72 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 25 ns (-15 speed grade) |
| Frecuencia de reloj máxima | [DATA_NEEDED: max fMAX for -2 grade] | — |
| Process Technology | CMOS | — |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | — |
| Encapsulado | 100-pin PQFP (R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Lead Pitch | 0.635 mm | — |
| Terminal Form | Gull-wing | — |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | — |
| Estado RoHS | [DATA_NEEDED: confirmed compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Altera (now Intel) |
| Family | — | MAX 5000 |
| Technology | — | CMOS |
| Logic Array Blocks (LABs) | — | 12 |
| External Clock Inputs | — | 1 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | EPROM (UV-erasable, OTP) |