EPM5192GC-1 vs EPM5192AJC-15 Comparación
Comparación detallada lado a lado de EPM5192GC-1 por Altera y EPM5192AJC-15 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192GC-1 | EPM5192AJC-15 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,85 | $9,85 |
| Family | MAX 5000 (Classic) | MAX 5000 |
| Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3,750 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | [DATA_NEEDED: user I/O count] |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (4.75 V to 5.25 V) |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Encapsulado | 100-pin Ceramic PGA (GC) | 84-pin PLCC (J-lead, ceramic, non-windowed) |
| Tipo de montaje | Through-Hole (PGA) | Surface Mount |
| Configuration Method | UV-Erase / One-Time Programmable | — |
| Interconnect | Peripheral Interconnect Array (PIA) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Capacity | — | 100% connectivity, sum-of-products PLA architecture |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Programmability | — | UV-erasable (windowed variant) / One-Time-Programmable |
| Toolchain | — | MAX+PLUS II |
| Recuento de pines | — | 84 |
| Speed Grades Available | — | -15, -20, -25 (this part: -15) |
| Configuration Memory | — | EPROM (UV-erasable) |