EPM5192GI-2 vs EPM5192GC-2 Comparación
Comparación detallada lado a lado de EPM5192GI-2 por Intel y EPM5192GC-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192GI-2 | EPM5192GC-2 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $61,00 | $92,00 |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable / OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 30 ns | 12 ns typical (-2 grade) |
| Frecuencia de reloj máxima | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | 5 V nominal |
| Operating Temperature Grade | Industrial | — |
| Encapsulado | 84-pin PGA (Pin Grid Array) | — |
| Package Code | PGA | — |
| Package Shape | Square | — |
| Terminal Form | PIN/PEG (through-hole) | — |
| Programming Method | UV-erase window (erasable) / OTP | — |
| Process Technology | CMOS | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) |
| Family | — | MAX 5000 |
| Logic Array Blocks | — | 16 (LABs of 16 macrocells each) |
| Usable I/O Pins | — | [DATA_NEEDED: exact user I/O count for PGA package] |
| Counter Frequency | — | 100 MHz minimum |
| Technology | — | CMOS EPROM |
| Programmable Technology | — | UV-erasable / one-time programmable |
| Programming Toolchain | — | Altera MAX+PLUS II |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Temperatura de funcionamiento | — | Commercial (0C to +70C) |
| Speed Grade | — | -2 |
| Tipo de montaje | — | Through-hole (PGA socket) |