EPM5192JC-1 vs EPM5192GC1 Comparación
Comparación detallada lado a lado de EPM5192JC-1 por Altera y EPM5192GC1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192JC-1 | EPM5192GC1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,40 | $24,50 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Technology | CMOS, UV-Erasable / OTP | — |
| Macrocells | 192 | — |
| Usable Gates | 3750 | 3,750 |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| User I/O Pins | 84 | — |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | Ceramic PGA (Pin Grid Array) |
| JEDEC Package Code | S-CQCC-J84 | — |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | — |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | — |
| Process | CMOS EPROM | — |
| I/O Standard | TTL/CMOS 5 V compatible | — |
| Macro Cells | — | 192 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Logic Elements | — | 192 macrocells with AND/OR array |
| Process Technology | — | EPROM-based CMOS |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| Número de pines | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Tipo de montaje | — | Through-hole (PGA) |
| Estado RoHS | — | unknown |
| Development Tool | — | Altera MAX+PLUS II |