EPM5192JC-2 vs EPM5192JC-1N Comparación
Comparación detallada lado a lado de EPM5192JC-2 por Altera y EPM5192JC-1N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192JC-2 | EPM5192JC-1N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,50 | $19,85 |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | 40 ns |
| Frecuencia de reloj máxima | 40 MHz | — |
| Process Technology | CMOS | — |
| Encapsulado | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | 84-pin Ceramic Quad Flat Pack (CQFP) |
| Tipo de montaje | Surface Mount | — |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Usable Gates | — | 3750 |
| External Clock Inputs (GCLK) | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| JEDEC Package Code | — | S-CQCC-J84 |
| Temperatura de funcionamiento | — | [DATA_NEEDED: industrial/commercial temperature range] |
| Programming Interface | — | JTAG / Altera ByteBlaster |