EPM5192JI-1 vs EPM5192JI-2 Comparación
Comparación detallada lado a lado de EPM5192JI-1 por Intel y EPM5192JI-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192JI-1 | EPM5192JI-2 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,40 | $9,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 12 |
| Propagation Delay (tPD) | 55 ns | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Encapsulado | 84-pin JLCC (Windowed ceramic J-lead) | JLCC-68 (J-Lead Ceramic) |
| Temperatura de funcionamiento | Industrial, -40 C to +85 C | 0C to +70C (commercial) |
| Configuration Memory | UV-erasable EPROM | — |
| Programming Method | External EPROM programmer (via programming hardware) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic JLCC, contains lead) |
| Speed Grade | -1 (slowest grade in EPM5192 family) | -2 |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array | — |
| Usable Gates | — | 5000 |
| Flip-Flops | — | 192 |
| Programming Technology | — | UV-Erasable EPROM |
| Architecture | — | Sum-of-products with Programmable Interconnect Array (PIA) |
| Tensión de alimentación | — | 5 V (typical) |
| Tipo de montaje | — | Surface Mount |
| Estado del ciclo de vida | — | Obsolete (legacy Altera MAX 5000 family) |