EPM5192LC-1 vs EPM5192LC-2 Comparación
Comparación detallada lado a lado de EPM5192LC-1 por Altera y EPM5192LC-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC-1 | EPM5192LC-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $7,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD / CPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| Número de pines | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | — |
| Propagation Delay | 25 ns | — |
| Frecuencia de reloj máxima | 50 MHz | — |
| Tensión de alimentación | 5 V nominal (4.75 V to 5.25 V) | 5 V (typical MAX 5000 family) |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | — |
| Estado RoHS | Non-compliant (ceramic LDCC with Pb-bearing terminations) | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Dedicated Input Pins | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns (typical, -2 speed grade) |
| Maximum Internal Frequency | — | 50 MHz |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS |
| Encapsulado | — | PQCC-84 (PLCC-84, J-lead, surface mount) |
| Programming | — | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) |