EPM5192LC-1 vs EPM5192LC-25 Comparación
Comparación detallada lado a lado de EPM5192LC-1 por Altera y EPM5192LC-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC-1 | EPM5192LC-25 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $55,00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD / CPLD | — |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| Número de pines | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | — |
| Propagation Delay | 25 ns | — |
| Frecuencia de reloj máxima | 50 MHz | — |
| Tensión de alimentación | 5 V nominal (4.75 V to 5.25 V) | 5 V (typical, MAX 5000) |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | -25 (25 ns) |
| Estado RoHS | Non-compliant (ceramic LDCC with Pb-bearing terminations) | Unknown (legacy ceramic package typically non-RoHS) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Encapsulado | — | JLCC-84 (ceramic J-lead chip carrier) |
| Tipo de montaje | — | Surface Mount |
| Programmable Technology | — | UV-erasable / OTP (EPROM-based) |
| Programming Interface | — | JTAG / Altera programming hardware (legacy) |
| I/O Standard | — | TTL-compatible |
| Configuration Memory | — | Non-volatile EPROM (on-chip) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |