EPM5192LC-1 vs EPM5192LC-2N Comparación
Comparación detallada lado a lado de EPM5192LC-1 por Altera y EPM5192LC-2N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC-1 | EPM5192LC-2N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $11,85 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD / CPLD | — |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| Número de pines | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Propagation Delay | 25 ns | — |
| Frecuencia de reloj máxima | 50 MHz | — |
| Tensión de alimentación | 5 V nominal (4.75 V to 5.25 V) | 5 V (typical) |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | -2 (tPD approximately 25 ns) |
| Estado RoHS | Non-compliant (ceramic LDCC with Pb-bearing terminations) | Compliant (per -N lead-free suffix) |
| Flip-Flops | — | 192 |
| Logic Elements | — | 192 macrocells (PAL/GAL-style AND-OR array) |
| Propagation Delay (typical) | — | 25 ns |
| Programmability | — | UV-erasable EPROM cell |
| Tipo de montaje | — | Surface Mount (LC package) |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |
| Programming Interface | — | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |