EPM5192LC1 vs EPM5192LC-1 Comparación
Comparación detallada lado a lado de EPM5192LC1 por Altera y EPM5192LC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC1 | EPM5192LC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,40 | $14,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | EPLD / CPLD |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | — |
| Encapsulado | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | — |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Frecuencia de reloj máxima | 50 MHz | 50 MHz |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS EPROM | — |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | — |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| JEDEC Package Code | S-PQCC-J84 | — |
| Logic Gates | — | 3750 (typical usable) |
| User I/O | — | 64 |
| Número de pines | — | 84 |
| Package Type | — | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | — | 25 ns |
| Tensión de alimentación | — | 5 V nominal (4.75 V to 5.25 V) |
| Technology | — | CMOS, UV-erasable / OTP EPROM cell |
| Temperatura de funcionamiento | — | 0C to +70C (commercial) |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |
| Speed Grade | — | -1 |