EPM570GT100C5N vs EPM240T100C5N Comparación
Comparación detallada lado a lado de EPM570GT100C5N por Intel y EPM240T100C5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM570GT100C5N | EPM240T100C5N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,05 | $4,65 |
| Series | MAX II | — |
| Logic Elements | 570 | — |
| Equivalent Macrocells | 440 | 192 |
| User I/O | 76 | — |
| LABs | 36 | — |
| Maximum Frequency | 304 MHz | — |
| Pin-to-Pin Delay | [DATA_NEEDED: tPD value] | — |
| User Flash Memory (UFM) | 8 Kbit | — |
| Operating Supply Voltage (VCCINT) | 2.5 V / 3.3 V | — |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS | — |
| Encapsulado | TQFP-100 | 100-pin TQFP (T100), 14x14 mm |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | 0 °C to +85 °C (commercial, 'C' suffix) |
| Programmability | Flash-based, non-volatile (ISP via JTAG) | — |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| Estado RoHS | Compliant | Compliant (lead-free) |
| Family | — | MAX II |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| On-Chip User Flash | — | 8 Kbits |
| Maximum User I/O Pins | — | 80 |
| Number of I/O Banks | — | 4 |
| Pin-to-Pin Delay (speed grade 5) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Process Technology | — | 0.18 µm, 6-layer-metal flash |
| Core Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |