EPM570T100A5N vs EPM570T100C4 Comparación
Comparación detallada lado a lado de EPM570T100A5N por Altera y EPM570T100C4 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM570T100A5N | EPM570T100C4 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,72 | $9,40 |
| Device Family | MAX II | — |
| Logic Elements | 570 | — |
| Macrocells | 440 | 440 |
| User I/O Pins | 76 | — |
| Number of Logic Array Blocks (LABs) | 57 | — |
| Encapsulado | 100-pin TQFP | TQFP-100 (T100), 14 x 14 mm |
| Pin-to-Pin Logic Delay (tPD) | 5.4 ns | — |
| Maximum Internal Frequency | 304 MHz | — |
| Core Supply Voltage (VCCINT) | 1.8 V (typical) | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Configuration Memory | On-chip non-volatile flash | — |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | JTAG (IEEE 1149.1) - ISP |
| Temperatura de funcionamiento | -40 °C to +125 °C (industrial) | 0C to +85C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant | Compliant |
| Family | — | MAX II |
| Logic Elements (LEs) | — | 570 |
| Maximum User I/O Pins (this package) | — | 80 |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.4 ns |
| User Flash Memory | — | 8 Kbits |
| General-Purpose SRAM | — | 4.4 Mbits |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Nivel MSL | — | [DATA_NEEDED: MSL Level] |
| On-chip Oscillator | — | Yes (3.3 MHz / 5.5 MHz selectable) |
| Internal Logic Analyzers / ISP | — | JTAG-based in-system programmable, no external boot PROM required |