EPM7128AET1100-7 vs EPM7128AETC100-10N Comparación
Comparación detallada lado a lado de EPM7128AET1100-7 por Intel y EPM7128AETC100-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteComparación de especificaciones
| Parámetro | EPM7128AET1100-7 | EPM7128AETC100-10N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,40 | $9,95 |
| Family | MAX 7000A (MAX 7000AE) | MAX 7000AE |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| User I/O Pins | 84 | — |
| Logic Elements / LABs | [DATA_NEEDED: LAB count for 7128A] | — |
| Speed Grade | -7 (5 ns pin-to-pin) | -10 |
| Supply Voltage VCC | 5.0 V (typical) | — |
| I/O Voltage Tolerance | 3.3 V / 5.0 V | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Encapsulado | TQFP-100 | TQFP-100 |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Programming Interface | IEEE 1149.1 JTAG / ByteBlaster | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 3 (168 hours, per JEDEC J-STD-020) | — |
| Estado RoHS | ROHS3 Compliant | — |
| Lead-Free | Yes | — |
| Process Technology | CMOS, EEPROM-based | CMOS EEPROM |
| Series | — | EPM7128AE |
| Logic Array Blocks | — | 16 |
| User I/Os | — | 84 |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Tolerance | — | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | [DATA_NEEDED: maximum toggle frequency] |
| Programming | — | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Architecture | — | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | — | Yes (33 MHz, -10 grade per PCI SIG 2.2) |