EPM7128AETC100-5N vs EPM7128AETC100-7N Comparación
Comparación detallada lado a lado de EPM7128AETC100-5N por Intel y EPM7128AETC100-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
EPM7128AETC100-5N ✓ ActivoComparación de especificaciones
| Parámetro | EPM7128AETC100-5N | EPM7128AETC100-7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,85 | $31,80 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | — |
| User I/Os | 84 | 84 |
| Logic Gates (typical) | 2,500 | — |
| Pin-to-Pin Logic Delay (tPD) | 5 ns | — |
| Maximum Operating Frequency | 192.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Bank Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 5V Tolerant Inputs | Yes (when VCCIO = 3.3 V) | — |
| Programmable Logic Type | EEPROM-based, in-system programmable | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) | JTAG (IEEE 1149.1) / ISP |
| Encapsulado | 100-pin TQFP | 100-TQFP |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tpd) | — | 7.5 ns |
| Counter Frequency (max) | — | 129.9 MHz |
| Internal Frequency (max) | — | 250 MHz |
| Core Supply Voltage | — | 3.3 V |
| Logic Family | — | CMOS |
| Recuento de pines | — | 100 |
| Process Technology | — | 0.30 µm EEPROM CMOS |