EPM7128ATC100-7F vs EPM7128ATI100-10 Comparación
Comparación detallada lado a lado de EPM7128ATC100-7F por Altera y EPM7128ATI100-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
EPM7128ATC100-7F NrndAltera
EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
EPM7128ATI100-10 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7128ATC100-7F | EPM7128ATI100-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $13,85 |
| Family | MAX 7000A | MAX 7000A (MAX II of MAX 7000 series) |
| Device | EPM7128A | — |
| Logic Elements / Macrocells | 128 macrocells | — |
| Logic Array Blocks (LABs) | 8 | — |
| Usable Gates | 2.5K | 2,500 |
| User I/O Pins | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) | — |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V (nominal 3.3 V) | — |
| I/O Voltage | 2.5 V / 3.3 V (MultiVolt) | — |
| Programmable Type | EEPROM (in-system programmable, non-volatile) | EE PLD (EEPROM-based, in-system programmable) |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP | — |
| Encapsulado | 100-pin TQFP (14x14 mm) | 100-pin TQFP (14x14 mm) |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (Industrial, 'I' suffix) |
| Process Technology | CMOS, EEPROM configuration | CMOS EEPROM |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (legacy part) |
| Series | — | MAX 7000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Number of I/O Pins | — | 68 |
| Maximum Frequency (fMAX) | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Standard | — | MultiVolt (2.5V / 3.3V / 5.0V tolerant) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |